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Design of Low-Power High-Speed 32×32 Multiplier (Electronics Project)

A low power multiplication algorithm and its VLSI architecture using a mixed number representation is proposed. The reduced switching activity and low power dissipation are achieved through the Sign-Magnitude (SM) notation for the multiplicand and through a novel design of the Redundant Binary (RB) adder and Booth decoder.

The high speed operation is achieved through the Carry- Propagation-Free (CPF} accumulation of the Partial Products (PP) by using the RB notation. Analysis showed that the switching activity in the PP generation process can be reduced on average by 90%. Compared to the same type of multipliers, the proposed design dissipates much less power and is 18% faster on average .

Introduction:
It has been shown that by the use of the SM notation for the multiplicand, the use of Two’s Complement (2’C) representation for the multiplier, and the use of RB representation for the PP accumulation, the Expected Switching Activity (ESA), and therefore the power dissipation, can be significantly reduced.

The ESA reduction occurs any time the negation of the multiplicand is needed in order to generate the PPs upon the radix-4 Booth’s algorithm. High speed operation is sustained through the RB notations for accumulating the PPs, since a CPF addition can be executed with RB numbers. The inputs and outputs of the multiplication unit are assumed to be in 2’C notation.

It is interesting to point out the fact that although the proposed algorithm and its VLSI architecture is complex in terms of the number conversions, it is more energy efficient and has an operating speed close to the Wallace tree architecture and faster than the other proposed multipliers.
Source: BITS-PILANI
Author: Sandeep Gupta

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