The P3RMA (Programmable, Parallel, and Predictable Random Memory Access) processor, currently being developed at Linköping University Sweden, is an attempt to solve the problems of parallel computing by utilizing a parallel memory subsystem and splitting the Continue reading
With the increasing gate density, the rising clock frequency, printed circuit board (PCB) level simultaneous switching noise (SSN) has become a major bottleneck for the Continue reading
Today’s consumer market is driven by technology innovations. Many technologies that were not available a few years ago are quickly being adopted into common use. Equipment for these services requires Continue reading
The WaitLess bus tracking device is a standalone system designed to display the real-time location(s) of the buses on Georgia Tech’s campus. The system will consist of Continue reading
There is a lot of literature already available describing well-structured approach for embedded design and implementation of Continue reading
In modern on-chip memories, an increasing demand for higher performance, lower power, reduced area, and improved robustness creates a rising need for advanced microarchitecture and circuit design techniques.
Particularly in large-signal multi-ported register files, these advanced design techniques include: Continue reading
Embedded microcomputers are used in a wide range of applications nowadays. Avionics is one of these areas and requires extra attention regarding reliability and determinism. Thus, these issues should also be born in mind in addition to performance when evaluating embedded microcomputers.
This master thesis suggests a framework for performance evaluation of two members of the PowerPC microprocessor family, namely the MPC5554 from Freescale and PPC440EPx from AMCC, and analyzes Continue reading
Routers are probably the most important component of a NoC, as the performance of the whole network is driven by the routers’ performance. Cost for the whole network in terms of area will also be minimised if the router design is kept small. A new application specific processor architecture for implementing NoC routers is proposed in this master thesis, which will be called μNP (Micro- Network Processor). The aim is to offer a solution in which Continue reading
The aim of this project is to demonstrate the incorporation of computer method in railway traffic control to improve, safety, speed of handling the traffic and also reliability. Here we employ the microprocessor (Intel 8085) to handle the signaling, track changing and gate operation and to monitoring the traffic. The system starts with the tracking if the train is sensed at the station side or starts with the gate operation (i.e. gate opening and closing) along with the track changing if the train is sensed at the gate side. Once the train arrival is sensed at a distance of about 3 kms the microprocessor performs the gate operation along with the track changing, the identification of the train is done at a distance of 3 kms accordingly the particular operation is performed by the processor. Depending upon the priority of the incoming train, the unengaged track is given for train halting.