We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems.
Serial link transceivers achieve high offchip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with high-speed, serial off-chip buses.
While synchronous transceivers commonly use multi-phase clocks to control the data multiplexing and demultiplexing, our clockless transceiver uses a token-ring architecture that eliminates complex clock generation and synchronization circuitry.
Furthermore, our clockless receiver dynamically self-adjusts its sampling rate to match the bit rate of the transmitter. Our SPICE simulations report that in a 0.18- um CMOS technology this transceiver design operates at up to 3-Gb/s and dissipates 77 mW of power with a 1.8-V supply voltage.
Introduction:
We describe the design of a high-speed, clockless, serial link transceiver. As the demand for off-chip bandwidth grows with on-chip operating frequency, high bit-rate I/O pins become increasingly necessary for inter-chip signaling interfaces in VLSI systems. While it is always possible to increase off-chip bandwidth by making buses wider with more I/O pins, it is often impractical due to cost and limits in packaging technology.
This suggests a chip design should efficiently utilize its existing I/O pins by driving them at high bit rates. An attractive high bit-rate I/O communication scheme, utilized in high-speed synchronous links, multiplexes and demultiplexes on-chip data onto a high-speed, off-chip serial bus. In this paper we propose an analogous scheme for asynchronous links.
Authors: John Teifel and Rajit Manohar
Source: Cornell University
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