VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking (IEEE Electronics Project)

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Owing to the usage of Internet, concerns about protecting and enforcing intellectual property (IP) rights of the digital content are mounting. Unauthorized replication and manipulation of digital content is relatively easy and can be achieved with inexpensive tools.

Digital rights management (DRM) systems address issues related to ownership rights of digital content. Various aspects of content management – namely, content identification, storage, representation, and distribution – and IP rights management are highlighted in DRM. Although unauthorized access of digital content is being prevented by implementing encryption technologies, these approaches do not prevent an authorized user from illegally replicating the decrypted content.

Digital watermarking is one of the key technologies that can be used in DRM systems for establishing ownership rights, tracking usage, ensuring authorized access, preventing illegal replication, and facilitating content authentication. Therefore, a two-layer protection mechanism utilizing both watermarking and encryption is needed to build effective DRM systems that can address IP rights and copyright issues. We recently designed a high-performance, high-throughput, and area-efficient very-large-scale (VLSI) architecture for the Rijndeal Advanced Encryption Standard (AES) algorithm. This architecture and corresponding chips will eventually lead to a complete hardware-based DRM system, the ultimate objective of our ongoing research.

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