Since a few years, flat screen TVs, such as LCD and plasma, has come to completely dominate the market of televisions. In a SoC solution for digital TVs, several processors are used to obtain a decent image quality.
Some of the processors need temporal information, which means that whole frames need to be stored in memory, which in turn motivates the use of SDRAM memory. When higher demands of resolution and image quality arrives, greater pressure is put on the performance of the SoC memory subsystem, to not become a bottleneck of the system.
In this master thesis project, a model of an existing SoC for digital TVs is used to benchmark and evaluate the performance of an SDRAM memory controller architecture study. The two major features are the ability to reorder transactions and the compatibility with DDR3.
By introducing reordering of transactions, the choice is given to the memory controller to service memory requests in an order that decreases bank conflicts and read/write turn arounds. Measurements show that a utilization of 86.5 % of the total available bandwidth can be achieved, which is 18.5 percentage points more, compared to an existing non reordering memory controller developed by NXP.
Source: Linköping University
Author: Winberg, Ulf