Routers are probably the most important component of a NoC, as the performance of the whole network is driven by the routers’ performance. Cost for the whole network in terms of area will also be minimised if the router design is kept small. A new application specific processor architecture for implementing NoC routers is proposed in this master thesis, which will be called μNP (Micro- Network Processor). The aim is to offer a solution in which there is a trade-off between the high performance of routers implemented in hardware and the high level of flexibility that could be achieved by loading a software that routed packets into a GPP. Therefore, a study including the design of a hardware based router and a GPP based router has been conducted.
In this project the first version of the μNP has been designed and a complete instruction set, along with some sample programs, is also proposed. The results show that, in the best case for all implementation options, μNP was 7.5 times slower than the hardware based router. It has also behaved more than 100 times faster than the GPP based router, keeping almost the same degree of flexibility for routing purposes within NoC.
Network-on-Chip (NoC) is a relatively new research field within System-on-Chip (SoC). Before NoC was considered, Intellectual Property (IP) cores were connected among each other through buses. This option is costly when many IP cores want to be interconnected and becomes very complex. Dedicated architectures and on-chip designs cannot support current development requirements and time-to market, that is why reusable components and scalable solutions are of great importance, . Therefore, taking some ideas from computer networks, for the NoC approach, IP cores were connected to a network of routers to allow the exchange of information between them. Such platform (NoC) architecture and design methodology is proposed in .
The router is considered to be the most important component in any network. Therefore, it can also be stated that a router is the most important part of a NoC.
A router’s job is to help deliver information (packets) from one IP core to another within the NoC. Routers are therefore interconnected with other routers and with one or many resources within the network. In the case of mesh topologies, the most widely used for NoC, the number of routers is equal to the number of IP cores.
Routers are the bottleneck of a NoC and as networks tend to be homogeneous (all routers in the network will most likely have the same design), if the performance of a router design is optimized, then the whole network’s performance will be increased.
As have been discussed, NoC borrowed some ideas from computer networks, so it seems appropriate to do the same now to try to improve NoC’s performance. Network Processors (NP) are specific purpose processors used for implementing routers in computer networks and can therefore become an inspiration for an onchip router design. Such router design is the goal of this study, and will be called Micro-Network Processor (μNP).
μNP will be designed as an ASP (Application Specific Processor) as high performance and small area is expected for the design. If a GPP (General Purpose Processor was used, the degree of flexibility achieved could be very high but the latency when routing and the area of the processor would be much larger than required for this application, as will be discussed further in this chapter.
Authors: Julia Martín Rovira, Francisco Manuel Fructuoso Melero
Source: Jönköping University