This project presents a Field Programmable Gate Array (FPGA) based embedded system which is used to achieve high speed segmentation of 3D images. Segmentation is performed using Expectation-Maximization with Maximization of Posterior Marginals (EM/MPM) Bayesian algorithm. In this system, the embedded processor controls a custom circuit which performs the MPM and portions of the EM algorithm.
The embedded processor completes the EM algorithm and also controls image data transmission between host computer and on-board memory. The whole system has been implemented on Xilinx Virtex 6 FPGA and achieved over 100 times improvement compared to standard desktop computing hardware.
Source: Purdue University
Author: Liu, Chao
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