Sleep apnea is a condition where people pause while breathing in their sleep; this can be of great concern for infants and prematurebabies. Current monitoring systems either require physical attachment to a user or may be unreliable.
This project is meant to develop a device that can accurately detect breathing through sound and issue appropriate warnings upon its cessation. The device produced is meant to be a standalone device and thus was developed as an embedded systems project on a Xilinx Spartan 6 FPGA.
One of the crucial points of the device is that it be accurate, with extremely little chance of false negatives and few false positives while detecting apnea events. The device must be easy to operate and setup. No special training should be required to use or maintain the device and setup requirements should be minimal and unobtrusive.
The device itself should be small in dimension not requiring large spaces and have few remote connections. The device should be powered from the wall with possible support for battery backup. To meet these needs some form of embedded system is desired.
The overall design involves acquiring sound from a microphone, this sound is then processed to detect breathing and a timer counts how long between breaths. When an apnea event occurs, longer than 20 seconds without breath, an alarm is sounded.
One of the first steps in the project’s design was a Matlab model created by Ricky Hennessy. This served as a proof of concept and a much easier platform to debug than methods used than hardware can easily provide.The program took in audio data from a microphone and detected the peaks in the signal, as seen in Figure 1 below. From the Matlab code a Simulink model was derived, the filtering portion of this code was used to produce the VHDL filter that will be discussed shortly.
The main hardware for the project is the ATLYS project board from Digilent, as seen in Figure 2. This board features a Xilinx Spartan 6 LX45 FPGA, of special use to the project was the chips DSP48A1 slices which allows for efficient implementation of digital filters.The ATLYS board also features an AC’97 codec, National Semiconductor LM4550, which ideally would be used to sample incoming audio. It has a USB port used to power the USB pre-amp for the microphone system. Primary power is provided by a 20 watt AC to DC converter. The board does get warm so ventilation needs to be provided for in the packaging.
The software part of the system is to be done using MicroBlaze. This is a microprocessor that is run on the FPGA and programmed using the Xilinx Embedded Develpment Kit. This is programmed using C with some slight modifications due to a more limited environment than a general computer system. MicroBlaze interacts with the hardware which is synthesized in the FPGA through a memory mapped interface. Figure 6 provides an overview for the software of the system.
The audio filter was developed in Simulink and exported as VHDL. This caused a number of problems during implementation. The first of which is that on a general purpose computer floating point numbers are perfectly reasonable when dealing with audio signals.
Microblaze is what is called a soft core processor, unlike other micro controllers it is only implemented in VHDL. This is provided by Xilinx as part of their development software as well as many other hardware components.
SYSTEM INTEGRATION AND TESTING:
The system was rather closely knit and thus integration was done over the course of development rather than entirely at the end . An example would be the input and output, these are related systems and can be used to verify each other.
The input and output systems are also crucial to the development and testing of the VHDL filter since signals needed to be given as input and verified on an oscilloscope through the output device. Once the input and output systems were in place the VHDL filter was inserted into the design, this also required the interrupt system to be in place to ensure the 8 kHz input.
I believe this project was rather successful, it was a difficult process and development was quite a bit slower than desired but the final product is rather close to the designed system. It could probably require a bit more fit and finish but the system is at least workable. An incoming signal is filtered for the desired range an envelope is created, peaks are detected and a timer is kept.
Mainly the problem is in that there has been no testing on sound from actual infants and that might require a change in the VHDL filter and audio setups. There is also a noticeable presence of false positives which is unacceptable for a final device. This is probably due to a lack of testing and calibration and could be remedied with more testing. The peak detection currently has a minimum level for peaks and this could be raised to reduce false positives but could also introduce a number of false positives and would vary depending upon audio input parameters.
A maximum level could also be added to reduce the impact of sudden noises not currently being filtered out. Averaging a number of past maximums to rule out infrequent behavior would also be helpful. The project could be simplified in two ways, first the proper usage of the AC’97 codec for data acquisition. This removes the need for the shifter circuit as well as some of the work arounds in the filter.
If this cannot be done then a cheaper board, without the audio codec, is recommended. Initially size of the design on the FPGA was a concern, but as implemented is not a current issue. The speed of the system is also not a great concern in the current implementation which works at 8 kHz and doesn’t require a great deal of computation. Of course if further analysis of the breathing is desired then these might become relevant concerns, though that would also require an overhaul of the filtering system or secondary processing of the initial samples.
Source: California Polytechnic State University
Author: Brian Berg