ABSTRACT
Processing and analysis of Very High Resolution (VHR) satellite images provide a mass of crucial information, which can be used for urban planning, security issues or environmental monitoring. However, they are computationally expensive and, thus, time consuming, while some of the applications, such as natural disaster monitoring and prevention, require high efficiency performance.
Fortunately, parallel computing techniques and embedded systems have made great progress in recent years, and a series of massively parallel image processing devices, such as digital signal processors or Field Programmable Gate Arrays (FPGAs), have been made available to engineers at a very convenient price and demonstrate significant advantages in terms of running-cost, embeddability, power consumption flexibility, etc.
In this work, we designed a texture region segmentation method for very high resolution satellite images by using the level set algorithm and the multi-kernel theory in a high-abstraction C environment and realize its register-transfer level implementation with the help of a new proposed high-level synthesis-based design flow. The evaluation experiments demonstrate that the proposed design can produce high quality image segmentation with a significant running-cost advantage.
BACKGROUND
The level set method refers to the class of active contour models that uses the implicit representation of the evolving curve instead of the parametric one, i.e., the Lagrangian framework and Eulerian framework. Its advantages include the following:
(1) It allows the texture of interest to be selected and segmented depending on the user requirements by providing a set of user-controlled parameters,
(2) It allows easier handling of complex shapes and topological changes.
LEVEL SET ALGORITHM DESCRIPTION
Figure 1. The D2Q5 Lattice Boltzmann Method (LBM) model
In our case, the D2Q5 (two dimensions and five discrete velocity directions) LBM lattice structure shown in Figure 1 is used for the solver of the proposed level set equation. The level set equation evolution equation can be expressed as follows.
DESIGN FLOW DESCRIPTION
Figure 2. High-Level Synthesis (HLS)-based design flow: “ * ” refers to the manual-necessary cycles
Figure 2 shows the proposed design flow. Considering most designs begin with the algorithm analysis, which requires a very high level environment to facilitate the descriptions of mathematical operations and the simulations of the model, we select MATLAB as the favorite user-level design environment for its advantages in the terms of vector processing and powerful built-in image processing tools. Once the algorithm is verified, we can start to prototype the algorithm for FPGA synthesis.
IMPLEMENTATION AND OPTIMIZATION
Figure 3. Block hierarchy comparison: (a) original version; (b) debugged version; and (c) Function Inline (FI) version
Figure 3a,b displays the block hierarchies before and after debugging. In this figure, an assignment is represented by a directed wire (e.g., from pow() to ImgSeg_Ori()), so we can find that the original version leads to only six assignments and increases to fifteen for the debugged version. Despite an optimization possibility by using function-level parallelism, due to the isolation of each sub-block, the optimizations available in the deeper loop and instruction levels are confined to the scope of the blocks even if some different block loops or operations are able to be more efficiently manipulated.
EXPERIMENT
Figure 6. Impact of the parameter α on the accuracy of the segmentation result
Figure 7. Impact of the parameter β on the accuracy of the segmentation result
In the experiment result analysis of Figure 6, we can see that a too low value of α (α = 0.5) leads to an over-segmentation, while a too high value (α = 10) decreases the precision of the result (under-segmentation). In Figure 7, we can also see that a too low value of β leads to an under-segmented result as the curve fails to detect the right contour. Therefore, we fixed α = 2 and β = 3.5. However, it should be noted that this configuration is obtained within double floating point numbers; for the single floating point and fixed point numbers, we changed α from 2 to 5 and 9, respectively.
CONCLUSIONS
In this paper, we implement an embedded VHR satellite image segmentation design. First of all, we select FPGAs as the target device for the desired design and built a novel dedicated design framework by using the HLS technique. The proposed design flow can effectively acceleratethe development cycles by facilitating the algorithm analysis, the design implementation and the exploration of design alternatives.
Next, an active contour model and its LBM-based solver are prototyped and analyzed as the target image segmentation algorithm in a math-convenient environment. The proposed algorithm has a high parallelism nature, which can greatly improve the design performance. During the implementing process, the design is optimized depending on the features of HLS. In the evaluation experiments, it is seen that the proposed design can produce a high quality image segmentation result in the nature or disaster images taken by IKONOS or GeoEye-1.
Compared to the reference implementations on the CPU or FPGA, the proposed design has a 5.29–14.21 × higher running time performance with a similar capacity in terms of maintainability. Therefore, it is concluded that the achievement of this paper has a great application prospect and potential in the remote sensing-based nature disaster prevention and monitoring.
Source: University Bourgogne
Authors: Chao Li | Souleymane Balla-Arabe | Dominique Ginhac | Fan Yang
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