A Low power fully operational digital hearing aid chip is proposed and implemented. The Σ-∆ ADC adopts the status controller to realize adaptive SNR technique without any external control.
To achieve both low power consumption and high programmability, dedicated low power DSP with 6 control parameters is designed. The heterogeneous Σ-∆ DAC reduces more power dissipation without performance degradation. The digital hearing aid system is fabricated in 0.18 µm CMOS technology, consumes less than 96 µW and has a die size of 2.8 mm x 1.1 mm.
In these days, the enormous attention of the bioelectronics system market requires new design methodologies to achieve both low power and high performance. Especially more and more people suffer from their hearing problems, and the number of people with some degree of hearing loss continuously increased every year.
According to this requirement, the development of the digital hearing aid system with low power consumption, more flexibility, small form factor and low cost is getting to achieve much attention. The previous studies had accomplished low power hearing aid system by adopting special CMOS process such as low-threshold voltage or by using a log-domain analog hearing aid with sub-threshold technique.
However, those approaches have some weaknesses to reduce power dissipation because of boosted supply voltage for analog blocks or signal processing with analog filters which dissipates high power. In this paper we present a fully operational one chip implementation of a digital hearing aid with less than 100 μW power consumption.
This chip is based on our previous low-power analog front-end circuit for digital hearing aid and a status controller, a low-power dedicated DSP and heterogeneous Σ-∆ DAC are integrated newly for the full function of digital hearing aid.
Source: The Pennsylvania State University
Authors: Sunyoung Kim , Namjun Cho , Seong-jun Song , Donghyun Kim , Kwanho Kim , Hoi-jun Yoo