Implementation of Pipelined Bit-parallel Adders (Electronics Project)

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Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied.

Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis.

The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.

Introduction:
Addition is one of the basic arithmetic operations in binary arithmetic by adding two binary numbers. An adder should be designed to meet the requirements of many modern devices: small chip area and high circuit speed.

Since high speed computer arithmetic units such as adders, multipliers and fast dividers that dominate the power dissipation and device complexity is dramatically increasing nowadays, low power design has come to the fore-front in addition to the two traditional issues mentioned above. Especially, the adder is critical in the aim to reduce overall power consumption since they are used for implementation of multipliers.

Bit-parallel addition can be performed using different structures on which different areas and latencies are yielded. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied.

This thesis work aims at comparing some adder structures with respect to their throughputs, areas and powers, and give a guide on which structure that yields the minimum power consumption for a given throughput.
Source: Linköping University
Author: Wei, Lan

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