Analog-to-digital converter (ADC) plays an important role in mixed signal processing systems. It serves as an interface between analog and digital signal processing systems. In the last two decades, circuits implemented in current-mode technique have drawn lots of interest for sensory systems and integrated circuits.
Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in low voltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement the pipelined ADC in SI technique and to optimize the pipelined ADC for low power.
The ADC has a stage resolution of 3 bits. The proposed architectures combine a differential sample-and-hold amplifier, current comparator, binary-to-thermometer decoder, a differential current-steering digital-to-analog converter, delay logic and digital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelined ADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics of ADC.
Source: Linköping University
Authors: Rajendran, Dinesh Babu