Since the discovery of carbon nanotubes (CNTs) by Iijima in 1991, significant progress has been achieved for both understanding the fundamental properties and exploring possible engineering applications. The possible application for nanoelectronic devices has been extensively explored since the demonstration of the first carbon nanotube transistors (CNTFETs) in 1998.
Carbon nanotubes are attractive for nanoelectronic applications due to its excellent electric properties. In a nanotube, low bias transport can be nearly ballistic across distances of several hundred nanometers. The conduction and valence bands are symmetric, which is advantageous for complementary applications. The bandstructure is direct, which enables optical emission, and finally, CNTs are highly resistant to electromigration.
Significant efforts have devoted to understand how a carbon nanotube transistor operates and to improve the transistor performance. It has been demonstrated that most CNTFETs to date operates like non-conventional Schottky barrier transistors, which results in quite different device and scaling behaviors from the MOSFET-like transistors.
Important techniques for significantly improving the transistor performance, including the aggressively scaling of the nanotube channel, integration of thin high-κ gate dielectric insulator, use of excellent source-drain metal contacts, and demonstration of the selfalign techniques, have been successfully developed. Very recently, a nanotube transistor, which integrates ultra-short channel, thin high-κ top gate insulator, excellent Pd sourcedrain contacts is demonstrated using a self-align technique. Promising transistor performance exceeding the state-of-the-art Si MOSFETs is achieved. The transistor has a near-ballistic source-drain conductance of 0.5 * e2 / h and delivers a current of 20 μA at |VG-VT| ~ 1 V.
In this work, numerical simulations are developed to explain experiments, to understand how the transistor operates and what controls the performance, and to explore the approaches to improve the transistor performance.
Source: HCM City University of Natural Sciences
Author: Dinh Sy Hien
- Fabrication and Modeling of Silicon Carbide (SiC) Bipolar Junction Transistors (ECE/EEE Project)
- Carbon Fiber Electronic Interconnects (Mechanical Project)
- Modeling and Experimental Techniques to Demonstrate Nanomanipulation With Optical Tweezers (Mechanical Project)
- Modeling and Optimization Techniques for Efficient Implementation of Parallel Embedded Systems (Electronics Project)
- Modeling of a Single-Phase Liquid Cooling System for Power Electronics Applications (Mechanical Project)
- Microprocessor based railway system
- Modeling of Two-Phase Heat Transfer in Chip-Scale Non-Uniformly Heated Microgap Channels (Mechanical Project)