High Level Model of IEEE 802.15.3c Standard and Implementation of a Suitable FFT on ASIC (Electronics Project)

Get this Project:

Fields with * are mandatory

A high level model of HSIPHY mode of IEEE 802.15.3c standard has been constructed in Matlab to optimize the wordlength to achieve a specific bit error rate (BER) depending on the application, and later an FFT has been implemented for different wordlengths depending on the applications. The hardware cost and power is proportional to wordlength.

However, the main objective of this thesis has been to implement a low power, low area cost FFT for this standard. For that the whole system has been modeled in Matlab and the signal to noise ratio (SNR) and wordlength of the system have been studied to achieve an acceptable BER. Later an FFT has been implemented on 65nm ASIC for a wordlength of 8, 12 and 16 bits. For the implementation, a Radix-8 algorithm with eight parallel samples has been adopted. That reduce the area and the power consumption significantly compared to other algorithms and architectures.

Moreover, a simple control has been used for this implementation. Voltage scaling has been done to reduce the power. The EDA synthesis result shows that for 16bit wordlength, the FFT has 2.64 GS/s throughput, it takes 1.439 mm2 area on the chip and consume 61.51mW power.
Source: Linköping University
Author: Ahmed, Tanvir

Download Project

>> 200+ Matlab Projects based on Control System for Final Year Students

>> 80+ Matlab Projects based on Power Electronics for Engineering Students

Get this Project:

Fields with * are mandatory

Leave a Comment

Your email address will not be published. Required fields are marked *