A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems (Computer Project)

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ABSTRACT

With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS) and CPU shut-down are the two most popular techniques used to design the algorithms.

In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework.

The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.

ADVANCES IN POWER-AWARE SCHEDULING

Figure 1. An example of power-aware scheduling using a slowed-down speed

Figure 1. An example of power-aware scheduling using a slowed-down speed

This process repeats, until all tasks are assigned a processor speed to run. For example, in Figure 1, there are six intervals, (0, 4), (2, 8), (0, 8), (2, 12), (7, 12) and (0, 12). The highest intensity ratio is the one of (0, 12), which is 0.5. Since the interval includes all of the three tasks, a processor speed of 0.5 is used to run all of them.

REAL-ENERGY

Figure 3. Real-Energy’s environment setup. DAQ data acquisition; DVS, dynamic voltage scaling

Figure 3. Real-Energy’s environment setup. DAQ data acquisition; DVS, dynamic voltage scaling

Figure 3 shows the environment’s outline. Our hardware platform subsystem includes a PYTHECT phyCOREr PXA255 rapid development kit, a desktop and a data acquisition (DAQ) USB-6800 from National Instruments. The rapid development kit is the target platform in our embedded development environment. The desktop is our host machine. The computer program is developed, compiled and linked on the host machine before it is downloaded to the target platform.

Figure 5. Energy consumption using dynamic voltage scaling (DVS)

Figure 5. Energy consumption using dynamic voltage scaling (DVS)

The CPU’s and the system-wide energy consumption are calculated according to the approach mentioned above. Figure 5 shows the normalized results for running these two tasks at the four supported frequency settings. It confirms that for Intel PXA255 using the lowest speed is not CPU energy efficient, and using a lower speed exhibits less efficiency in saving the system-wide energy.

A CASE STUDY

Figure 8. CPU energy consumption for the RM and EDF algorithms

Figure 8. CPU energy consumption for the RM and EDF algorithms

The experimental results for DVS algorithms are presented in two categories, RM or EDF, as shown in Figure 8. In RM, the results of using lppsRM and ccRm are normalized and compared to the result of using a fixed static speed without utilizing an on-line slack. These results are compared at four workload conditions, where the percentage of slack means the average ratio between the actual execution time (by adjusting the number of loops) and the WCET.

Figure 9. System-wide energy consumption for the RM and EDF algorithms

Figure 9. System-wide energy consumption for the RM and EDF algorithms

We are also interested in how much of the total energy is consumed by the system when only the CPU is working. This information is useful to analyze the energy usage contributed by the idle memory, leakage currents, etc. Figure 9 shows the measured system-wide energy consumption for using the RM and EDF algorithms when running CPU-bound tasks.

CONCLUSION

In designing power-aware algorithms, it is always important to know the real performance, because so many factors can affect the results. This motivates us to design a unified framework for the evaluations in spite of the complication. Our work does a comprehensive job of completing such a tool in hardware and software. We not only use the tool for evaluation, we also can use it to test the implementation of algorithms in order to find out practical issues.

In our case study, while the effectiveness of the DVS technique for reducing the CPU’s energy consumption is shown, it also confirms that it does not effectively reduce the system’s energy consumption. The CPU shut-down is a simple and effective one to save the system’s energy consumption, but so far, it is only applicable for running tasks with a predefined release time. Otherwise, the CPU does not know when to wake up to continue the execution.

We do not implement or evaluate the algorithms using a critical speed. The use of the critical speed requires a continuous range of the CPU speed, which is unpractical today on any platform. Therefore, there has been a focus on thermal-aware scheduling recently. Our framework can be used for the topic by finding a way to measure a CPU’s temperature. The Real-Energy framework is not specifically hardware and software dependent.

The OS, Linux, with programming in C is widely used in embedded systems. The development kit and data collection device and their replacements are easily found on the market. It does not need any hardware modification. When a newer generation of hardware components appears, they can be easily used in the framework, as long as they have a similar architecture and functionalities.

Source: University of Houston
Authors: Jian (Denny) Lin | Albert M. K. Cheng | Wei Song

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