Independent Study on Porting Amber CPU to DE1-SOC and Altera Bus (Electronics Project)

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INTRODUCTION:

The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM® v2a instruction set architecture (ISA) and is therefore supported by the GNU toolset. The Amber project is a complete embedded system implemented on the Xilinx Spartan -6 SP605 FPGA development board.

The project is hosted on opencores.org. The project provides a complete hardware and software development system based around the Amber processor core. Several applications, with C source code, are provided as examples of what the system can be used for. The embedded system includes the Amber core and several peripherals, including a UART, a timer and an Ethernet MAC.

FPGA:

The FPGA board used for the course of this project was DE1-SOC, which is equipped with Altera Cyclone® V SE 5CSEMA 5F31C6N device. The FPGA is part of the Cyclone V SoC family from the Altera family. The photograph for DE1-SOC board is shown in Figure 1. The DE1-SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.

Figure 1: DE1-SoC development board.

Figure 1: DE1-SoC development board.

AMBER CORE:

There are two versions of the core provided in the Amber project. The project focuses on implementation of Amber 23 system. Amber 23 has following features:

  • 3-stage pipeline.
  • 32-bit Wishbone system bus.
  • Unified instruction and data cache, with write through and a read-miss replacement policy. The cache can have 2, 3, 4 or 8 ways and each way is 4kB.
  • Multiply and multiply-accumulate operations with 32-bit inputs and 32-bit output in 34 clock cycles using the Booth algorithm. This is a small and slow multiplier implementation.
  • Little endian only, i.e. Byte 0 is stored in bits 7:0 and byte 3 in bits 31:24.

The following diagram shows the data flow through the 3-stage core.

Amber 23 Core Pipeline Stages.

Amber 23 Core Pipeline Stages.

 AMBER FPGA SYSTEM:

The FPGA system included with the Amber project is a complete embedded processor system which  included all peripherals needed to run Linux, including UART, timers and an Ethernet (MII) port. The following diagram shows the entire system.

Amber FPGA System.

Amber FPGA System.

SYSTEM ADDRESSES:

Address Map:

The comprehensive system level address map is shown in Table 3. Note that Amber system on Xilinx FPGA has an external DDR memory and hence has 128Mbytes of address space for main memory. The Amber system ported on Altera FPGA in this project doesn’t have external main memory but on-chip M9K RAM. Hence, the address space for main memory is reduced to 16kBytes.

Table 3: System Address Map.

Table 3: System Address Map.

SOFTWARE SUPPORT:

Till this point, all discussion Amber FPGA system was made from hardware point of view. This section discusses all the software tools and support necessary to run bootloader, standalone application or Linux.

Installing the Compiler:

Tests need to be compiled before running on board. To do this, it is necessary to install
a GNU cross-compiler. The easiest way to install the GNU tool chain is to download a readymade package. Code Sourcery provides a free one.

Select the GNU/Linux version and then the IA32 GNU/Linux Installer. Once the package is installed,  add  the following to <.bashrc> file, where the PATH is set to where you install the Code Sourcery GNU package.

p-15320--independent-study-on-porting-amber4

Bootloader:

The boot loader is used to download longer applications onto the FPGA development board via the UART port and using Putty on a host Windows PC.

  • Load an executable file
  • Load binary file to a particular address
  • Execute an already loaded application by jumping to that address
  • Read/Write to main memory
  • View core status

Standalone Application:

Once bootloader is run, then the processor would do the initialization and jump to main memory depending on the option selected. Then any standalone application can be run. Figure 23 shows a hello-world application.

Figure 23: Hello -World Application Code.

Figure 23: Hello -World Application Code.

CONCLUSION

I have made progress in both sections of the independent study the hardware implementation of the Amber System and the software programming section. I have created an Amber FPGA system for Altera that also contains memory initialization file for bootloader code.

I have familiarized myself with the Quartus tools and the software tools for cross-compiling application for Amber . I am currently stuck with an obstacle , which I believe I would be able to solve soon and accelerate progress. I hope to continue this next semester.

Source: Cornell University
Author: Mohammad Saifee Dohadwala

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