The audio power amplifier plays an essential role in every system that generates audible sound. General power amplifies are voluminous, heavy, expensive, unreliable and have very poor energy utilization, all due to a low efficiency.
In the last few years the use of digital technology in audio electronics has become widespread and, nowadays, there is an increasing interest in the development of completely digital audio systems. Moreover, the growing market demand for small size multimedia systems with high output power and large number of audio channels is driving the need for high efficiency power amplifiers.
Recently, a great effort has been made to develop fully digital power amplifiers, usually referred to as power DACs. These amplifiers convert the PCM (Pulse Coded Modulation) digital signal into a sigma-delta modulated 1-bit data stream or a PWM (Pulse Width Modulation) signal. The high frequency two-level signal is then amplified using an open loop power buffer and low-pass filtered.
This approach is relatively simple, but the output analog signal is adversely affected by supply noise and non-idealities within the power buffer. A good performance can be obtained using more complex digital structures and algorithms for noise and distortion reduction. However, a more efficient approach for building a low cost power DAC relies on the use of a feedback power buffer. A single chip power DAC with a feedback power buffer has been recently proposed.
The digital input signal is converted in a noise-shaped one-bit signal Pulse Density Modulation (PDM) modulator. The PDM bit stream directly feeds a class-D amplifier, and a simple LC filter reconstructs the audio signal. In this thesis we proposed CMOS digital audio amplifier based on delta sigma modulator a power efficient switching (class D) output-stage with out intermediate frequency. The technology is UMC 0.18 micron CMOS.
Various topologies of digital audio amplifiers are investigated at 0.18 micron. Therefore we designed the digital Amplifier in 0.18m standard digital CMOS Process with operation frequency 2.75 KHz, the amplifier can operate from 1V to 1.8V. UMC 0.18 micron offers Low and Zero threshold voltage transistors, in addition to the Regular threshold voltage transistors.
However previously not much work have been done or reported a CMOS power amplifier in particular low voltage. As a supply voltage is reduced to 1V, the performance of the amplifier, such as the output power and the efficiency are degraded. In this thesis the design considerations of CMOS amplifier under low supply voltage and power are detailed.
The total harmonic distortion at the load is less than 0.07% with a dynamic range (DR) is 85dB. We can obtain an efficiency of 76% with the load resistance of 4.3 ohm. The maximum out put power is this case can be 350mW from a single 1.8 power supply. In this work we have demonstrated the implementation of Class-D amplifier
with high end audio performance in low voltage environment.
Author: Amleset, Kelati